• http://www.voipac.com/
• Marvell PXA270 and ARM Microprocessor Tips

voipac-pxa270-src.zip

voipac-pxa270-docs.zip

voipac-pxa270-bin.zip

PXA270M DIMM Module Basic specification:

• PXA270M / 312MHz
• 64MB NAND Flash (16bit)
• 64MB SDRAM (32bit)
• Audio AC'97 with controller and support for touchscreen
• 10/100 Mbps Ethernet
• 121 GPIOs
• 200pin SODIMM connector
• JTAG connector pads
• Power supply 3.3V with flexible PMIC
• Dimensions 67.6 x 38.0mm
• 0°C to +70°C commercial temperature range

PXA270M DIMM Module Pro specification:

• PXA270M / 520MHz (by default set to 312MHz)
• 128MB NAND Flash (16bit)
• 128MB SDRAM (32bit)
• Audio AC'97 with controller and support for touchscreen
• 10/100 Mbps Ethernet
• 121 GPIOs
• 200pin SODIMM connector
• JTAG connector pads
• Power supply 3.3V with flexible PMIC
• Dimensions 67.6 x 38.0mm
• 0°C to +70°C commercial temperature range

make menuconfig

Target Architecture (arm)
Target Architecture Variant (xscale)
Target ABI (OABI)
Build options
[*] Enable compiler cache
System configuration
  (em5) System hostname
  (ttyS0) Port to run a getty (login prompt) on 
  Baudrate to use (38400)
Filesystem images
[*] jffs2 root filesystem
[*]   Do not use Cleanmarker
Kernel  
  Kernel binary format (zImage)  ---> 

make uclibc-menuconfig

Target Architecture Features and Options
  [*]   Target CPU has a floating point unit (FPU)
Networking Support
  [*]     Remote Procedure Call (RPC) support

make linux-menuconfig

Прошиваем обновленный загрузчик через JTAG.

Удобно это делать на отладочной baseboard: pxa270_dimm_base_board-datasheet.pdf pxa270_dimm_base_board-schematic.pdf

К плате подключаем JLINK, 12V и COM-порт.

На компьютер устанавливаем openocd:

 $ sudo apt install openocd
 $ openocd --version
   Open On-Chip Debugger 0.12.0

Запускаем отладчик с правильным конфигурационным файлом.

В разных JLINK сделанных на чипе ftdi может быть по-разному распаян пин RST. Поэтому пробуем разные значения 'ftdi layout_init' пока не заработает.

vpac270_openocd_v0.12.cfg

#Voipac PXA270 Script
 
telnet_port     4444
gdb_port        3333
adapter driver  ftdi
transport select jtag
ftdi vid_pid 0x0403 0x6010
ftdi channel 1
#ftdi layout_init 0x0018 0x00fb
ftdi layout_init 0x0078 0x007b
ftdi layout_signal nTRST -data 0x0010 -oe 0x0010
ftdi layout_signal nSRST -data 0x0040 -oe 0x0040	
 
# JTAG speed (kHz) – adjust as needed
adapter speed 1000
 
# Variables for PXA270
if { [info exists CHIPNAME] } {    
   set _CHIPNAME $CHIPNAME    
} else {     
   set _CHIPNAME pxa270
}
 
if { [info exists ENDIAN] } {    
   set _ENDIAN $ENDIAN    
} else {     
   set _ENDIAN little
}
 
if { [info exists CPUTAPID ] } {
   set _CPUTAPID $CPUTAPID
} else {
   set _CPUTAPID 0x79265013
}
 
adapter srst delay 260
jtag_ntrst_delay 0
 
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst separate
 
# JTAG scan chain
set _TARGETNAME $_CHIPNAME.cpu
jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
 
# Target creation
target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME
 
# Work area configuration
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x5c000000 -work-area-size 0x10000 -work-area-backup 0
 
# Flash banks (CFI driver remains valid)
flash bank flash0 cfi 0x00000000 0x2000000 2 2 $_TARGETNAME
flash bank flash1 cfi 0x02000000 0x2000000 2 2 $_TARGETNAME

  $ openocd -f vpac270_openocd_v0.12.cfg
  Open On-Chip Debugger 0.12.0
  Licensed under GNU GPL v2
  For bug reports, read
  	http://openocd.org/doc/doxygen/bugs.html
  Info : pxa270.cpu: hardware has 2 breakpoints and 2 watchpoints
  Info : Listening on port 6666 for tcl connections
  Info : Listening on port 4444 for telnet connections
  Info : clock speed 1000 kHz
  Info : JTAG tap: pxa270.cpu tap/device found: 0x79265013 (mfg: 0x009 (Intel), part: 0x9265, ver: 0x7)
  Info : starting gdb server for pxa270.cpu on 3333
  Info : Listening on port 3333 for gdb connections

For a flow-through DMA read/write from/to an internal peripheral, use the following settings for the DMA controller register bits:

Write to device:
DCMDx[FLYBYS] and DCMDx[FLYBYT] = 0
DSADRx[SRCADDR] = memory address
DTADRx[TRGADDR] = internal peripheral address
DCMDx[INCSRCADDR] = 1
DCMDx[INCTRGADDR] = 0
DCMDx[FLOWSRC] = 0
DCMDx[FLOWTRG] = 1

Read to memory:
DCMDx[FLYBYS] and DCMDx[FLYBYT] = 0
DSADRx[SRCADDR] = internal peripheral address
DTADRx[TRGADDR] = memory address
DCMDx[INCSRCADDR] = 0
DCMDx[INCTRGADDR] = 1
DCMDx[FLOWSRC] = 1
DCMDx[FLOWTRG] = 0

All companion-chip-related transfers must use 64-bit aligned addresses for both source and target locations.

Restricting memory addresses to 8-byte boundaries can be helpful because the DMA controller encounters overhead while it works with misaligned data. Align the source and target addresses to 32-byte boundaries for optimal DMA controller and memory controller performance.

By default, during data transfers the DMA controller forces the least significant three bits of all external addresses to zeros and the least significant two bits of all peripheral addresses to zeros. Software must activate the alignment register to activate byte-aligned addressing.

Companion Chip to Memory:

Source Alignment (Bytes) : 8
Target Alignment (Bytes) : 8
DCMD [IncSrcAddr] (Binary) : 0 or 1
DCMD [IncTrgAddr] (Binary) : 1
DCMD[Width] (Binary) : 00

The companion chip or external peripheral must be connected as a variable-latency I/O memory.

If either DCMDx[IncSrcAddr] or DCMDx[IncTrgAddr] is set, then the DMA controller increments the source or target address, after each bursting transaction, by a number equal to the transaction burst size (8, 16 or 32 bytes) or DCMDx[Len]. The latter is used if DCMDx[Len] is less than the burst size.

DCMD_WIDTH must be 0b00 for memory-to-memory moves or companion-chip-related operations.

—

Состояние регистров DMA смотри в debugfs: /debug/pxa_dma/channels/0/state

Большинство полезных функций уже определены в файлах

/arch/arm/plat-pxa/dma.c 
/arch/arm/plat-pxa/include/plat/dma.h

так что изобретать свои велосипеды нет необходимости.