SPASCHARM

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====== Voipac PXA270 Baseboard ======

  * http://www.voipac.com/ 
  * [[http://www.lancesimms.com/PXA270Tips.html|Marvell PXA270 and ARM Microprocessor Tips]]

{{equipment:embedded:voipac_pxa270_27m-dmm-144_l.jpg?200|}} {{equipment:embedded:voipac_pxa270_27m-dmm-144_l_b.jpg?200|}}

{{ :equipment:embedded:voipac-pxa270-src.zip |}}

{{ :equipment:embedded:voipac-pxa270-docs.zip |}}

{{ :equipment:embedded:voipac-pxa270-bin.zip |}}

PXA270M DIMM Module Basic specification:
  * PXA270M / 312MHz
  * 64MB NAND Flash (16bit)
  * 64MB SDRAM (32bit)
  * Audio AC'97 with controller and support for touchscreen
  * 10/100 Mbps Ethernet
  * 121 GPIOs
  * 200pin SODIMM connector
  * JTAG connector pads
  * Power supply 3.3V with flexible PMIC
  * Dimensions 67.6 x 38.0mm
  * 0°C to +70°C commercial temperature range

PXA270M DIMM Module Pro specification:
  * PXA270M / 520MHz (by default set to 312MHz)
  * 128MB NAND Flash (16bit)
  * 128MB SDRAM (32bit)
  * Audio AC'97 with controller and support for touchscreen
  * 10/100 Mbps Ethernet
  * 121 GPIOs
  * 200pin SODIMM connector
  * JTAG connector pads
  * Power supply 3.3V with flexible PMIC
  * Dimensions 67.6 x 38.0mm
  * 0°C to +70°C commercial temperature range

===== buildroot config =====
make menuconfig
<code>
Target Architecture (arm)
Target Architecture Variant (xscale)
Target ABI (OABI)
Build options
[*] Enable compiler cache
System configuration
  (em5) System hostname
  (ttyS0) Port to run a getty (login prompt) on 
  Baudrate to use (38400)
Filesystem images
[*] jffs2 root filesystem
[*]   Do not use Cleanmarker
Kernel  
  Kernel binary format (zImage)  ---> 
</code>

make uclibc-menuconfig
<code>
Target Architecture Features and Options
  [*]   Target CPU has a floating point unit (FPU)
Networking Support
  [*]     Remote Procedure Call (RPC) support
</code>

make linux-menuconfig

===== Flash with JTAG =====
Прошиваем обновленный загрузчик через JTAG.

Удобно это делать на отладочной baseboard:
{{ :equipment:embedded:pxa270_dimm_base_board-datasheet.pdf |}} {{ :equipment:embedded:pxa270_dimm_base_board-schematic.pdf |}}

К плате подключаем JLINK, 12V и COM-порт.

На компьютер устанавливаем openocd:
   $ sudo apt install openocd
   $ openocd --version
     Open On-Chip Debugger 0.12.0

В отдельном окне запускаем minicom или miniterm
     pyserial-miniterm /dev/ttyUSB2 38400
     minicom -D /dev/ttyUSB2  -b 38400
   
Запускаем отладчик с правильным конфигурационным файлом.

:!: В разных JLINK сделанных на чипе ftdi может быть по-разному распаян пин RST.
Поэтому пробуем разные значения 'ftdi layout_init' пока не заработает.

<file cfg vpac270_openocd_v0.12.cfg>
#Voipac PXA270 Script

telnet_port     4444
gdb_port        3333
adapter driver  ftdi
transport select jtag
ftdi vid_pid 0x0403 0x6010
ftdi channel 1
#ftdi layout_init 0x0018 0x00fb
ftdi layout_init 0x0078 0x007b
ftdi layout_signal nTRST -data 0x0010 -oe 0x0010
ftdi layout_signal nSRST -data 0x0040 -oe 0x0040	

# JTAG speed (kHz) – adjust as needed
adapter speed 1000

# Variables for PXA270
if { [info exists CHIPNAME] } {    
   set _CHIPNAME $CHIPNAME    
} else {     
   set _CHIPNAME pxa270
}

if { [info exists ENDIAN] } {    
   set _ENDIAN $ENDIAN    
} else {     
   set _ENDIAN little
}

if { [info exists CPUTAPID ] } {
   set _CPUTAPID $CPUTAPID
} else {
   set _CPUTAPID 0x79265013
}

adapter srst delay 260
jtag_ntrst_delay 0

#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst separate

# JTAG scan chain
set _TARGETNAME $_CHIPNAME.cpu
jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID

# Target creation
target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME

# Work area configuration
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x5c000000 -work-area-size 0x10000 -work-area-backup 0

# Flash banks (CFI driver remains valid)
flash bank flash0 cfi 0x00000000 0x2000000 2 2 $_TARGETNAME
flash bank flash1 cfi 0x02000000 0x2000000 2 2 $_TARGETNAME

</file>


    $ openocd -f vpac270_openocd_v0.12.cfg
    Open On-Chip Debugger 0.12.0
    Licensed under GNU GPL v2
    For bug reports, read
    	http://openocd.org/doc/doxygen/bugs.html
    Info : pxa270.cpu: hardware has 2 breakpoints and 2 watchpoints
    Info : Listening on port 6666 for tcl connections
    Info : Listening on port 4444 for telnet connections
    Info : clock speed 1000 kHz
    Info : JTAG tap: pxa270.cpu tap/device found: 0x79265013 (mfg: 0x009 (Intel), part: 0x9265, ver: 0x7)
    Info : starting gdb server for pxa270.cpu on 3333
    Info : Listening on port 3333 for gdb connections


Подключаемся к консоли отладчика и загружаем в память u-boot: 

{{ :equipment:embedded:vpac270_x-boot_u-boot.zip |}}

    > telnet localhost 4444

    Trying 127.0.0.1...
    Connected to localhost.
    Escape character is '^]'.
    Open On-Chip Debugger
    > reset halt       
        JTAG tap: pxa270.cpu tap/device found: 0x79265013 (mfg: 0x009 (Intel), part: 0x9265, ver: 0x7)
        Bad value '00' captured during DR or IR scan:
         check_value: 0x02
         check_mask: 0x07
        JTAG error while writing DCSR
        target halted in ARM state due to debug-request, current mode: Supervisor
        cpsr: 0x080000d3 pc: 0x00000000
        MMU: disabled, D-Cache: disabled, I-Cache: disabled
        (processor reset)
    > load_image /tftpboot/u-boot-1.1.2-vpac4.bin 0x5c010000
        51568 bytes written at address 0x5c010000
        downloaded 51568 bytes in 0.555464s (90.662 KiB/s)
    > resume 0x5c010000  
    
Успеваем переключиться на окно с minicom/miniterm и нажать любую клавишу. 

Должны увидеть приглашение командной строки u-boot:

U-Boot 1.1.2-vpac4 (Feb 26 2009 - 15:19:32)

    U-Boot code: 5C010000 -> 5C01C970  BSS: -> 5C020454
    RAM Configuration:
    Bank #0: a0000000 128 MB
    Bank #1: 80000000 128 MB
    Flash: 64 MB
    dm9000 i/o: 0x8000300 (32bit), id: 0x90000a46 
    MAC: 00:0d:15:00:a2:74
    Hit any key to stop autoboot:  0 
    u-boot> 


Use TFT to download first stage boot loader x-load.bin and write it to flash at offset 0.

  u-boot> erase all
  u-boot> tftp x-load.bin
  u-boot> cp.b a1000000 0 400


NOTE: During erase some blocks may fail to erase, those are bad blocks which may appear.

Download second stage bootloader and write it to flash at offset 0x800.

  u-boot> tftp u-boot-1.1.2-vpac4.bin
  u-boot> cp.b $(fileaddr) 800 $(filesize)


After power cycling baseboard, the first stage X-Loader and next u-boot bootloader should come up.


Или одним файлом сразу оба загрузчика:

  set serverip 172.22.0.101
  set ipaddr 172.22.0.123
  tftp x.img
  erase 1:0-
  cp.b $(fileaddr) 0 $(filesize)
===== DMA =====

==== Приотритеты каналов ====
^Set ^Channels ^Priority ^Number of Times Served^
|  0  | 0, 1, 2, 3, 16, 17, 18, 19  |  I (High)  |  4/8  |
|  1  | 4, 5, 6, 7, 20, 21, 22, 23  |  II  |  2/8  | 
|  2  | 8, 9, 10, 11, 24, 25, 26, 27 |  III  |  1/8  |
|  3  | 12, 13, 14, 15, 28, 29, 30, 31 |  IV  |  1/8  |

==== Flow-through DMA ====
For a flow-through DMA read/write from/to an internal peripheral, use the following settings for the DMA
controller register bits:
<code>
Write to device:
DCMDx[FLYBYS] and DCMDx[FLYBYT] = 0
DSADRx[SRCADDR] = memory address
DTADRx[TRGADDR] = internal peripheral address
DCMDx[INCSRCADDR] = 1
DCMDx[INCTRGADDR] = 0
DCMDx[FLOWSRC] = 0
DCMDx[FLOWTRG] = 1

Read to memory:
DCMDx[FLYBYS] and DCMDx[FLYBYT] = 0
DSADRx[SRCADDR] = internal peripheral address
DTADRx[TRGADDR] = memory address
DCMDx[INCSRCADDR] = 0
DCMDx[INCTRGADDR] = 1
DCMDx[FLOWSRC] = 1
DCMDx[FLOWTRG] = 0
</code>

All companion-chip-related transfers must use 64-bit aligned addresses for both source and target
locations.

Restricting memory addresses to 8-byte boundaries can be helpful because the DMA controller
encounters overhead while it works with misaligned data. Align the source and target addresses to
32-byte boundaries for optimal DMA controller and memory controller performance.

By default, during data transfers the DMA controller forces the least significant three bits of all
external addresses to zeros and the least significant two bits of all peripheral addresses to zeros.
Software must activate the alignment register to activate byte-aligned addressing.


**Companion Chip to Memory:**

Source Alignment (Bytes) : 8 \\
Target Alignment (Bytes) : 8 \\
DCMD [IncSrcAddr] (Binary) : 0 or 1 \\
DCMD [IncTrgAddr] (Binary) : 1 \\
DCMD[Width] (Binary) : 00

The companion chip or external peripheral must be connected as a variable-latency I/O memory.

If either DCMDx[IncSrcAddr] or DCMDx[IncTrgAddr] is set, then the DMA controller
increments the source or target address, after each bursting transaction, by a number equal to the
transaction burst size (8, 16 or 32 bytes) or DCMDx[Len]. The latter is used if DCMDx[Len] is
less than the burst size.

DCMD_WIDTH must be 0b00 for memory-to-memory moves or companion-chip-related operations.

---
===== Под Linux =====
Состояние регистров DMA смотри в debugfs: /debug/pxa_dma/channels/0/state 

Большинство полезных функций уже определены в файлах
  /arch/arm/plat-pxa/dma.c 
  /arch/arm/plat-pxa/include/plat/dma.h
так что изобретать свои велосипеды нет необходимости.
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