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Set | Channels | Priority | Number of Times Served |
---|---|---|---|
0 | 0, 1, 2, 3, 16, 17, 18, 19 | I (High) | 4/8 |
1 | 4, 5, 6, 7, 20, 21, 22, 23 | II | 2/8 |
2 | 8, 9, 10, 11, 24, 25, 26, 27 | III | 1/8 |
3 | 12, 13, 14, 15, 28, 29, 30, 31 | IV | 1/8 |
For a flow-through DMA read from an internal peripheral, use the following settings for the DMA controller register bits:
DCMDx[FLYBYS] and DCMDx[FLYBYT] = 0 DSADRx[SRCADDR] = memory address DTADRx[TRGADDR] = internal peripheral address DCMDx[INCSRCADDR] = 1 DCMDx[INCTRGADDR] = 0 DCMDx[FLOWSRC] = 0 DCMDx[FLOWTRG] = 1