Voipac PXA270 Baseboard

http://www.voipac.com/

Marvell PXA270 and ARM Microprocessor Tips

PXA270M DIMM Module Basic specification:

PXA270M / 312MHz

64MB NAND Flash (16bit)

64MB SDRAM (32bit)

Audio AC'97 with controller and support for touchscreen

10/100 Mbps Ethernet

121 GPIOs

200pin SODIMM connector

JTAG connector pads

Power supply 3.3V with flexible PMIC

Dimensions 67.6 x 38.0mm

0°C to +70°C commercial temperature range

PXA270M DIMM Module Pro specification:

PXA270M / 520MHz (by default set to 312MHz)

128MB NAND Flash (16bit)

128MB SDRAM (32bit)

Audio AC'97 with controller and support for touchscreen

10/100 Mbps Ethernet

121 GPIOs

200pin SODIMM connector

JTAG connector pads

Power supply 3.3V with flexible PMIC

Dimensions 67.6 x 38.0mm

0°C to +70°C commercial temperature range

buildroot config

make menuconfig

Target Architecture (arm)
Target Architecture Variant (xscale)
Target ABI (OABI)
Build options
[*] Enable compiler cache
System configuration
(em5) System hostname
(ttyS0) Port to run a getty (login prompt) on
Baudrate to use (38400)
Filesystem images
[*] jffs2 root filesystem
[*] Do not use Cleanmarker
Kernel
Kernel binary format (zImage) --->

make uclibc-menuconfig

Target Architecture Features and Options
[*] Target CPU has a floating point unit (FPU)
Networking Support
[*] Remote Procedure Call (RPC) support

make linux-menuconfig

Pxa270 DMA

32 DMA channels, DMA[31:0]

supports flow-through and fly-by transfer

32 channels, 68 PBP (peripherial-bus peripherals) requests, 3 IBP (internal-bus peripherals, only quick-capture interface in this chip) requests, and 3 external device requests.

A companion chip is defined as a device that has the ability to control the external bus, whereas an external peripheral must be controlled by the memory controller.

Приотритеты каналов

Set	Channels	Priority	Number of Times Served
0	0, 1, 2, 3, 16, 17, 18, 19	I (High)	4/8
1	4, 5, 6, 7, 20, 21, 22, 23	II	2/8
2	8, 9, 10, 11, 24, 25, 26, 27	III	1/8
3	12, 13, 14, 15, 28, 29, 30, 31	IV	1/8

Flow-through DMA

For a flow-through DMA read/write from/to an internal peripheral, use the following settings for the DMA controller register bits:

Read:
DCMDx[FLYBYS] and DCMDx[FLYBYT] = 0
DSADRx[SRCADDR] = memory address
DTADRx[TRGADDR] = internal peripheral address
DCMDx[INCSRCADDR] = 1
DCMDx[INCTRGADDR] = 0
DCMDx[FLOWSRC] = 0
DCMDx[FLOWTRG] = 1
Write:
DCMDx[FLYBYS] and DCMDx[FLYBYT] = 0
DSADRx[SRCADDR] = internal peripheral address
DTADRx[TRGADDR] = memory address
DCMDx[INCSRCADDR] = 0
DCMDx[INCTRGADDR] = 1
DCMDx[FLOWSRC] = 1
DCMDx[FLOWTRG] = 0