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Предыдущая версия справа и слева Предыдущая версия Следующая версия | Предыдущая версия | ||
equipment:embedded:voipac_pxa270_baseboard [2012/04/24 13:48] sergey |
equipment:embedded:voipac_pxa270_baseboard [2025/02/20 12:29] (текущий) |
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Строка 3: | Строка 3: | ||
* http://www.voipac.com/ | * http://www.voipac.com/ | ||
* [[http://www.lancesimms.com/PXA270Tips.html|Marvell PXA270 and ARM Microprocessor Tips]] | * [[http://www.lancesimms.com/PXA270Tips.html|Marvell PXA270 and ARM Microprocessor Tips]] | ||
+ | |||
+ | {{equipment:embedded:voipac_pxa270_27m-dmm-144_l.jpg?200|}} {{equipment:embedded:voipac_pxa270_27m-dmm-144_l_b.jpg?200|}} | ||
+ | |||
+ | {{ :equipment:embedded:voipac-pxa270-src.zip |}} | ||
+ | |||
+ | {{ :equipment:embedded:voipac-pxa270-docs.zip |}} | ||
+ | |||
+ | {{ :equipment:embedded:voipac-pxa270-bin.zip |}} | ||
+ | |||
+ | PXA270M DIMM Module Basic specification: | ||
+ | * PXA270M / 312MHz | ||
+ | * 64MB NAND Flash (16bit) | ||
+ | * 64MB SDRAM (32bit) | ||
+ | * Audio AC'97 with controller and support for touchscreen | ||
+ | * 10/100 Mbps Ethernet | ||
+ | * 121 GPIOs | ||
+ | * 200pin SODIMM connector | ||
+ | * JTAG connector pads | ||
+ | * Power supply 3.3V with flexible PMIC | ||
+ | * Dimensions 67.6 x 38.0mm | ||
+ | * 0°C to +70°C commercial temperature range | ||
+ | |||
+ | PXA270M DIMM Module Pro specification: | ||
+ | * PXA270M / 520MHz (by default set to 312MHz) | ||
+ | * 128MB NAND Flash (16bit) | ||
+ | * 128MB SDRAM (32bit) | ||
+ | * Audio AC'97 with controller and support for touchscreen | ||
+ | * 10/100 Mbps Ethernet | ||
+ | * 121 GPIOs | ||
+ | * 200pin SODIMM connector | ||
+ | * JTAG connector pads | ||
+ | * Power supply 3.3V with flexible PMIC | ||
+ | * Dimensions 67.6 x 38.0mm | ||
+ | * 0°C to +70°C commercial temperature range | ||
===== buildroot config ===== | ===== buildroot config ===== | ||
Строка 10: | Строка 44: | ||
Target Architecture Variant (xscale) | Target Architecture Variant (xscale) | ||
Target ABI (OABI) | Target ABI (OABI) | ||
+ | Build options | ||
+ | [*] Enable compiler cache | ||
System configuration | System configuration | ||
(em5) System hostname | (em5) System hostname | ||
(ttyS0) Port to run a getty (login prompt) on | (ttyS0) Port to run a getty (login prompt) on | ||
Baudrate to use (38400) | Baudrate to use (38400) | ||
+ | Filesystem images | ||
+ | [*] jffs2 root filesystem | ||
+ | [*] Do not use Cleanmarker | ||
Kernel | Kernel | ||
Kernel binary format (zImage) ---> | Kernel binary format (zImage) ---> | ||
Строка 26: | Строка 65: | ||
</code> | </code> | ||
- | ===== Pxa270 DMA ===== | + | make linux-menuconfig |
- | * 32 DMA channels, DMA[31:0] | + | |
- | * supports flow-through and fly-by transfer | + | |
- | * 32 channels, 68 PBP (peripherial-bus peripherals) requests, 3 IBP (internal-bus peripherals, only quick-capture interface in this chip) requests, and 3 external device requests. | + | |
- | A **companion chip** is defined as a device that has the ability to | ||
- | control the external bus, whereas an external peripheral must be controlled by the memory | ||
- | controller. | ||
==== Приотритеты каналов ==== | ==== Приотритеты каналов ==== | ||
Строка 46: | Строка 80: | ||
controller register bits: | controller register bits: | ||
<code> | <code> | ||
- | Read: | + | Write to device: |
DCMDx[FLYBYS] and DCMDx[FLYBYT] = 0 | DCMDx[FLYBYS] and DCMDx[FLYBYT] = 0 | ||
DSADRx[SRCADDR] = memory address | DSADRx[SRCADDR] = memory address | ||
Строка 55: | Строка 89: | ||
DCMDx[FLOWTRG] = 1 | DCMDx[FLOWTRG] = 1 | ||
- | Write: | + | Read to memory: |
DCMDx[FLYBYS] and DCMDx[FLYBYT] = 0 | DCMDx[FLYBYS] and DCMDx[FLYBYT] = 0 | ||
DSADRx[SRCADDR] = internal peripheral address | DSADRx[SRCADDR] = internal peripheral address | ||
Строка 64: | Строка 98: | ||
DCMDx[FLOWTRG] = 0 | DCMDx[FLOWTRG] = 0 | ||
</code> | </code> | ||
+ | |||
+ | All companion-chip-related transfers must use 64-bit aligned addresses for both source and target | ||
+ | locations. | ||
+ | |||
+ | Restricting memory addresses to 8-byte boundaries can be helpful because the DMA controller | ||
+ | encounters overhead while it works with misaligned data. Align the source and target addresses to | ||
+ | 32-byte boundaries for optimal DMA controller and memory controller performance. | ||
+ | |||
+ | By default, during data transfers the DMA controller forces the least significant three bits of all | ||
+ | external addresses to zeros and the least significant two bits of all peripheral addresses to zeros. | ||
+ | Software must activate the alignment register to activate byte-aligned addressing. | ||
+ | |||
+ | |||
+ | **Companion Chip to Memory:** | ||
+ | |||
+ | Source Alignment (Bytes) : 8 \\ | ||
+ | Target Alignment (Bytes) : 8 \\ | ||
+ | DCMD [IncSrcAddr] (Binary) : 0 or 1 \\ | ||
+ | DCMD [IncTrgAddr] (Binary) : 1 \\ | ||
+ | DCMD[Width] (Binary) : 00 | ||
+ | |||
+ | The companion chip or external peripheral must be connected as a variable-latency I/O memory. | ||
+ | |||
+ | If either DCMDx[IncSrcAddr] or DCMDx[IncTrgAddr] is set, then the DMA controller | ||
+ | increments the source or target address, after each bursting transaction, by a number equal to the | ||
+ | transaction burst size (8, 16 or 32 bytes) or DCMDx[Len]. The latter is used if DCMDx[Len] is | ||
+ | less than the burst size. | ||
+ | |||
+ | DCMD_WIDTH must be 0b00 for memory-to-memory moves or companion-chip-related operations. | ||
+ | |||
+ | --- | ||
+ | ===== Под Linux ===== | ||
+ | Состояние регистров DMA смотри в debugfs: /debug/pxa_dma/channels/0/state | ||
+ | |||
+ | Большинство полезных функций уже определены в файлах | ||
+ | /arch/arm/plat-pxa/dma.c | ||
+ | /arch/arm/plat-pxa/include/plat/dma.h | ||
+ | так что изобретать свои велосипеды нет необходимости. | ||
+ | |||
+ |